Part 01: Proposal and Overview. Dual Modulus Prescaler Using Current Mode Logic Goals 2.5 GHz Operation 8/9 Dual Modulus 0.18uM BSIM 3 Model. - ppt download
D FLIP-FLOP
Help me calculate the device size of CML/SCL latch design and simulate the gain of it | Forum for Electronics
Analysis and Design of High-Speed CMOS Frequency Dividers
PPT - Advantages of Using CMOS PowerPoint Presentation, free download - ID:3409185
Performance evaluation of the low-voltage CML D-latch topology - ScienceDirect
Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
A Dynamic Current Mode D-Flipflop for High Speed Application
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
Energy Efficient High-Speed Links Electrical and Optical Interconnect Architectures to Enable Tera-Scale Computing
Design of Low Power and High-Speed Cmos D Flipflop using Supply Voltage Level (SVL) Methods
PDF) Low-power high-speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices
An active inductor employed CML latch for high speed integrated circuits | SpringerLink
adding reset function to D Flip FLOP | Forum for Electronics
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
Design of Low Power and High-Speed Cmos D Flipflop using Supply Voltage Level (SVL) Methods
High Speed Digital Blocks
adding reset function to D Flip FLOP | Forum for Electronics
Figure 5.21 from Cmos Logic and Current Mode Logic 5.1 Introduction | Semantic Scholar
